On-Chip ESD Protection for Integrated Circuits
Discussing ESD protection circuit design problems from an IC designer's perspective, this book provides the materials needed by a circuit designer for designing ESD protection circuits, including: testing models and standards adopted by US Department of Defense, EIA/JEDEC, ESD Association, Automotive Electronics Council, International Electrotechnical Commission, etc; ESD failure analysis, protection devices, and protection of sub-circuits; whole-chip ESD protection and ESD-to-circuit interactions; advanced low-parasitic compact ESD protection structures for RF and mixed-signal ICs; and mixed-mode ESD simulation-design methodologies for design prediction ESD-to-circuit interactions.An IC Design Perspective Albert Z.H. Wang. BJT effect as illustrated in Figure 3.11, where the nominal current gain remains good in a limited range of Ic beyond that p drops dramatically. At low-current region, decrease in p is due to extra baseanbsp;...
| Title | : | On-Chip ESD Protection for Integrated Circuits |
| Author | : | Albert Z.H. Wang |
| Publisher | : | Springer Science & Business Media - 2002-01-31 |
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